Note that we are no longer adding the clock period to the required time. Required Time = CLK delay till FF2/CP + Hold requirement of FF2 With clock delays in place, data path delay isĬLK delay till FF1/CP + CLK->Q delay of FF1 + Comb path delay Arrival time = CLK delay till FF1/CP + CLK->Q delay of FF1 + Comb path delayĬlock path delay is CLK delay till FF2/CP. Data launched from launching flop is allowed to arrive at the input of the second flop only after a delay greater than its hold requirement so that it is properly captured. In simple terms, this makes sure the launched data does not arrive at the capture point too soon. lib file for the hold time values for pin D relative to clcok pin CP of the flip flop type of FF2). Hence the minimum delay requirement for the timing path is that the path to D should at least take more time than the hold time requirement of the flop FF2, so as not to corrupt the data. If the Data launched by FF1 reaches D of FF2 fast enough, it may be captured at the same clock edge A by the flop FF2. ThFF2 is the library hold time value of flop FF2. it is checking for the minimum delay the data should take to arrive at the second flop for the circuit to function correctly. Here you are verifying that the data is not captured at FF2/D on launching edge A of the CLK. If data arrives later than the clock path delay calculated above, the data won’t be captured at edge B.įrom above, it is clear that setup analysis checks for the maximum allowable delay for the timing path. So the required time for data arrival at FF2/D is Clock period + CLK delay till FF2/CP- TsFF2. Data at FF2/D should be stable for at least TsFF2 before the clock edge. Now, we should also take into account the setup requirement of FF2. Required Time = Clock period + CLK delay till FF2/CP. So the actual datapath delay is: CLK delay till FF1/CP + CLK->Q delay of FF1 + Comb path delayĪnd the actual clock path delay is: CLK delay till FF2/CP. So in setup check, we say a violation has occured if the data path delay is more than one clock cycle.Ĭlock has insertion delays. So we need to add one clock cycle to the clock path delay to get the Required Time.ĭata launched at FF1/CP should arrive at FF2/D in one clock period. However, we are checking the setup at the clock edge B. In analysis, we call this the Arrival Time. Now let us calculate the delay encountered by data and clock while reaching FF2. The data path of the timing circuit is through CP of FF1 to D of FF2. ie, CLK arrives at CP of FF1 & FF2 at 0 delay, edges coinciding. the flipflops have no setup and hold time requirements and clock is ideal. We will take up a register to register path (2 above) for explanation.įor ease of understanding, let us decide every component in the circuit is ideal. Input to output port through purely combinational logic. Timing paths can be the following types:Ĥ. Now, let us see what is meant by setup analysis for a timing path. Hold time is the minimum amount of time the data signal should be held steady after the clock event so that the data are reliably sampled. Setup time is the minimum amount of time the data signal should be held steady before the clock event so that the data are reliably sampled by the clock. However, the other terminology is more common.įirst a recap of the setup and hold time requirement of a flipflop. PT aptly calls them max and min delay analysis. The setup and hold violation checks done by STA tools are slightly different. We are used to the definitions of setup and hold times for a single flipflop. It is easy to get confused with the definitions of setup and hold violations.
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